FIG. 6 is a schematic configuration diagram showing an example of a drive circuit 1 of a related art which turns on/off a power element 2 such as an IGBT. The drive circuit 1 plays a role of turning on/off a drive signal applied to the gate of the IGBT (power element) 2 and thus controlling a main current flow between the collector and the emitter of the IGBT 2. A current Ic supplied to a load (RL) connected between a main power supply 3 and the IGBT 2 is controlled in accordance with the on/off of the IGBT 2.
Schematically, the drive circuit 1 includes a first semiconductor switching element Q1 and a second semiconductor switching element Q2 which are connected in series and provided between a power supply terminal (Vcc) of a power supply 4 and a ground terminal (GND). Further, the drive circuit 1 includes a third semiconductor switching element Q3 and a fourth semiconductor switching element Q4 which are connected in series and provided between the power supply terminal (Vcc) of the power supply 4 and the ground terminal (GND). A series connection point (node P1) between the first and second semiconductor switching elements Q1, Q2 is connected to the gate of the IGBT 2 via a gate resistor RG. A series connection point (node P2) between the third and fourth semiconductor switching elements Q3, Q4 is connected to the emitter of the IGBT 2.
The first to fourth semiconductor switching elements Q1, Q2, Q3, Q4 are each formed of, for example, a MOS-FET and constitute a switch matrix circuit in which the first to fourth semiconductor switching elements are turned on/off in association with one another and thus turn the IGBT 2 on/off under the control of a control circuit 5. The control circuit 5 turns on/off the first to fourth semiconductor switching elements Q1, Q2, Q3, Q4 in association with one another in accordance with a control signal SG supplied from the outside, thereby controlling on/off of the IGBT 2.
FIG. 7 shows operation timings which represent state changes in respective portions of the drive circuit 1 according to the control signal SG and voltage changes in the IGBT 2. In FIG. 7. V(P1) represents the voltage change in the node P1, V(E) represents the voltage change in the emitter (node P2) of the IGBT 2, V(G) represents the voltage change in the gate of the IGBT 2, and Vge represents the voltage change between the gate and the emitter of the IGBT 2.
As shown in FIG. 7, the drive circuit 1 positively or negatively biases the gate emitter voltage Vge of the IGBT 2 according to the control signal S thereby turning the IGBT 2 on/off. That is, the drive circuit 1 turns on each of the first and fourth semiconductor switching elements Q1, Q4 and turns off each of the second and third semiconductor switching elements Q2, Q3, thereby setting the voltage of the node P1 to a power supply voltage Vcc and setting the voltage of the node P2 to a voltage (0 V) of the ground terminal (GND). Thus, the drive circuit 1 applies the voltage (power supply voltage Vcc) of the node P1 to the gate of the IGBT 2, the emitter of which is set to 0 V, via the gate resistor RG, thereby positively biasing the IGBT 2. Consequently, the IGBT 2 is turned on by the positive bias (+Vcc) between the gate and the emitter thereof.
The drive circuit 1 turns off each of the first and fourth semiconductor switching elements Q1, Q4 and turns on each of the second and third semiconductor switching elements Q2, Q3, thereby setting the voltage of the node P1 to 0 V and setting the voltage of the node P2 to the power supply voltage Vcc. Thus, the drive circuit 1 grounds the gate of the IGBT 2, the emitter of which is set to the power supply voltage Vcc, via the gate resistor RG, thereby negatively biasing the IGBT 2. Consequently, the IGBT 2 is turned off by the negative bias (−Vcc) between the gate and the emitter thereof. The drive circuit 1 configured in this manner is described in detail in, for example, Japanese Patent No. 5011585.
The drive circuit 1 disclosed in Japanese Patent No. 5011585 can turn the IGBT 2 on/off by positively or negatively biasing the IGBT 2 using only the positive power supply voltage Vcc which is outputted from the power supply 4. Thus, this drive circuit is superior in terms of not requiring a negative power supply. However, the drive circuit 1 of the related art is configured to apply the voltage V(P1) of the node P1 to the gate of the IGBT 2 via the gate resistor RG, thereby charging/discharging a gate capacitor of the IGBT 2. Accordingly, there arises the defect that a switching loss at the turn-on and off times of the IGBT 2 is large.
In this respect, Japanese Patent No. 5011585 discloses that the switching loss at the turn-on/off times of the IGBT 2 is reduced by shifting the on/off timings of the first to fourth semiconductor switching elements Q1, Q2, Q3, Q4 therebetween. However, in the case of shifting the on/off timings of the first to fourth semiconductor switching elements Q1, Q2, Q3, Q4 therebetween, there arises the new problem that the configuration of the control circuit 5 is complicated.
In the drive circuit 1 of the related art, the IGBT 2 is turned off by merely applying the constant negative bias voltage (−Vcc) to the IGBT 2. Thus, when an operation voltage threshold value Vth of the IGBT2 changes with temperature change at the time of turning the IGBT 2 on, a time required for charging the gate capacitor of the IGBT 2 via the gate resistor RG, which is so-called a gate charge time, changes undeniably. As a result, the turn-on timing of the IGBT 2 shifts with a change in the gate charge time, and thus the IGBT 2 turns on at an unpreferable timing. In other words, the on/off timings of the IGBT 2 change undeniably by being affected by the temperature dependency of the on/off operating condition of the IGBT 2.